1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for a high accuracy analog circuit, and more particularly, to a semiconductor integrated circuit having protection elements for protecting MOS transistors in the high accuracy analog circuit from plasma damage occurring during the manufacturing processes of the semiconductor integrated circuit.
2. Description of the Related Art
Recent semiconductor technologies have rapidly promoted thin filming of semiconductor integrated circuits. Particularly, in MOS (Metal Oxide Semiconductor) type semiconductor integrated circuits or CMOS (Complementary MOS) type semiconductor integrated circuits technologies, thin filming for a thickness of gate insulating film has rapidly developed together with rapid developments of fining for a size or a length of the gate.
Generally, plasma processes, such as plasma etching, sputtering or plasma chemical vapor deposition (CVD), are used during manufacturing of MOS or CMOS type semiconductor integrated circuits. In the plasma process, electric charges are generated and concentrated on a gate electrode due to a charge-up phenomenon. The concentrated charge is supplied to a gate insulating film that is provided under a gate electrode, as a surge voltage. This generates various defects of the gate insulating film, such as degradations due to an increase of density of a surface level or dielectric breakdown.
When the plasma damage occurs at a gate insulating film, element characteristics of the gate insulating film have fluctuated or broken down. Thus, such a semiconductor integrated circuit may not be used because it has been lost reliability. In particular, a tolerance for the fluctuation of the element characteristic is much more severe for a MOS analog circuit than a MOS digital circuit, because the MOS analog circuit may use pairing or analogousness of elements. For instance, if a pairing (ΔVth) of a threshold voltages (Vth) of a semiconductor integrated circuit fluctuates more than several milli-volts (mV), it may not be used as a MOS analog circuit, because the pairing of threshold voltages is an important characteristic for a MOS analog circuit.
To avoid plasma damage during manufacturing processes, a semiconductor integrated circuit having a protection element have conventionally been proposed. The inventor also has proposed such a semiconductor integrated circuit having protection element for avoiding plasma damage. FIG. 10 illustrates a circuit diagram of a semiconductor integrated circuit 110 for an operational amplifier proposed in a previous application by the same inventor.
As illustrated in FIG. 10, the semiconductor integrated circuit 110 comprises a group of MOS type transistors TR101, TR102 of the same characteristics and wiring films 111. Although the group includes more than two MOS type transistors, for simplification of explanation, this instance shows two MOS type transistors TR101 and TR102. To prevent the transistor characteristics from fluctuating influences due to the plasma damage, each gate electrode of the MOS transistor TR101, TR102 is respectively provided a damage relieving circuit of two diodes 103-104 and 101-102 between a supply voltage Vcc and a ground 119.
Recently, integration technologies for a large scale integrated circuit (LSI) of MOS type or CMOS type have advanced thin filming of a gate insulating film. Thus, an insulation breakdown voltage of a gate insulating film also has rapidly dropped. Consequently, a relationship between an insulation breakdown voltage of a gate insulating film and a breakdown voltage of a protection diode in a reverse direction has been changed. FIG. 11 that has been described in an article “ESD in Silicon Integrated Circuits” issued by John Wiley & Sons in 1995 shows a relationship between a PN junction breakdown voltage depending upon a thickness of a gate film and a gate insulating breakdown voltage depending upon a thickness of a gate film.
In FIG. 11, a solid line (a) indicates a PN junction breakdown voltage depending upon a thickness of a gate film, i.e., a PN junction breakdown voltage between a source/drain layer of a MOS transistor and a substrate. A dotted line (b) indicates a gate insulation breakdown voltage depending upon a thickness of the gate insulating film. As shown in FIG. 11, even when a thickness of a gate film is reduced, a reduction of a PN junction breakdown voltage is not lowered very much. On the contrary, a gate insulation breakdown voltage rapidly falls even when a thickness of a gate film is gradually reduced. When the thickness of a gate film is reduced lower than 3.8 nano-meters (nm), the relationship between the gate breakdown voltage and the PN junction breakdown voltage is reversed. Thus, the PN junction breakdown voltage becomes higher than the gate insulation break down voltage. This generates such a defect that a gate insulation breakdown occurs prior to an occurrence of a break-down of the protection diodes due to plasma damage during a manufacture of MOS or CMOS.
Accordingly, when a thin filming of a gate layer thickness has been promoted, the conventional MOS or CMOS gate protection techniques have defects and problems that a gate insulating film has broken down before protection elements are broken down by plasma damage during manufacturing processes of the semiconductor integrated circuit.